Cambridge, UK, 10/03/2024 – Low Drop-Out (LDO) voltage regulators are essential core IP blocks found in many of today’s electronic devices, such as smartphones, wearable tech and battery-powered applications. At Agile Analog, we offer a range of configurable, multi-node LDOs to meet the exact requirements of our customers.
Key factors when selecting LDOs
The key requirements for any LDO design are the input supply voltage, desired output voltage and output current. In addition to these, there are several other key factors to consider when choosing LDOs in order to ensure that the LDO addresses the specific needs of your application.
Capless vs externally biased: In an ideal world, every LDO would be capless, reducing the device pin count, PCB area and cost. However, capless LDOs have limitations in terms of transient response and output voltage accuracy. In applications requiring high performance, or response to rapid transients, the additional flexibility and control of an externally biased LDO may be more appropriate.
Load and line regulation: LDOs have limitations in their ability to achieve perfect load and line regulation. Load regulation refers to how well the LDO maintains a constant output voltage as the load current changes, while line regulation measures the LDO's sensitivity to changes in the input voltage. Whilst high line and load regulation is usually desirable, this comes at the expense of area and increased quiescent current consumption. However, for applications where precise output voltage control is critical, even under varying load conditions, an LDO with excellent load and line regulation characteristics is vital.
Noise and PSRR: LDOs generate a certain amount of noise, which can be detrimental to sensitive components or circuits. LDOs may also be susceptible to noise and interference from the input voltage, which can degrade the quality of the output signal. Power Supply Rejection Ratio (PSRR) is a measure of how well an LDO can reject noise and disturbances from the input voltage. A high PSRR indicates that the LDO is effective at filtering out unwanted signals and maintaining a clean output. If the load is sensitive to noise, an LDO with low output noise and high PSRR is crucial. The circuitry required for a low noise and/or high PSRR LDO often needs additional area, external biasing capacitors and increased current. This can potentially introduce instability. It is therefore important to carefully evaluate the trade-offs in such a design.
Quiescent current: Also known as standby current, this is the current consumed by an LDO when there is no load connected. A low quiescent current is required in applications where power consumption is a key issue, such as battery-powered devices or portable electronics. Low quiescent current LDOs typically are compromised in their ability to regulate, and in their noise and PSRR specifications, but the reduced current consumption makes them essential in power sensitive applications.
Finding the right LDO that fits
Selecting the right LDO IP can be complex. With a diverse range of needs it has not been easy for chip designers to find LDO IP solutions that fit their exact requirements.
At Agile Analog, as a result of our unique Composa technology, we can automatically generate analog IP that matches the customer’s specifications, on any foundry or process. We have a collection of LDOs supporting different input voltage, output voltage and output current requirements.
Programmable LDOs: These enable the output voltage to be set digitally via control inputs. These are often used in applications with multiple power modes, involving one voltage in active mode and another in sleep mode.
Fixed output LDOs: These provide a fixed output voltage. These are easy to use and are normally seen in applications where a specific voltage is needed.
Ultra-low drop-out LDOs: These are designed to have less than 200mV of dropout. These are ideal for applications requiring high efficiency through minimal voltage loss between input and output, and are commonly employed to provide additional power supply rejection in high current applications where the input supply may be coming from a noisy switching converter.
Low noise LDOs: These provide a stable output with minimal electrical noise. These are typically used in sensitive analog circuits, RF circuits and other noise-sensitive applications.
High PSRR LDOs: These are developed to suppress input power supply variations and noise. These are for applications where the quality of the incoming power supply is not reliable and the driven circuits are sensitive, for example, in communication systems.
Capless LDOs: These can deliver their required performance without an off-chip output capacitor. These are ideal for applications with limited space, such as smartphones and wearable devices.
Externally biased LDOs: These require external capacitors at the output and occasionally at the input to ensure stability. These are for sensitive analog circuits, RF applications and high-power digital systems.
High current LDOs: These can supply higher output current compared to standard LDOs. These are used in applications requiring substantial current, like providing the digital supply for a microprocessor.
Low quiescent current LDOs: These are designed to consume very low quiescent current when not under load. These are appropriate for always-on domains in battery-operated devices where power efficiency is critical.
At Agile Analog, multiple different LDOs can also be combined with our bandgap reference, power-on-reset and sensors to provide a complete PMU (Power Management Unit) solution for your application. Please check out our website.
Chris Morrison, Director of Product Marketing, Agile Analog