Highlights:
• 5th generation of network-on-chip interconnect silicon IP technology
• Up to 5X faster physical convergence vs manual physical iterations
• Enables customers to achieve PPA goals within schedule and budget constraints
CAMPBELL, Calif., February 22, 2023 (GLOBE NEWSWIRE) – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced the launch of Arteris FlexNoC 5 physically aware network-on-chip (NoC) interconnect IP. FlexNoC 5 enables SoC architecture teams, logic designers and integrators to incorporate physical constraint management across power, performance and area (PPA) to deliver a physically aware IP connecting the SoC. This technology enables 5X faster physical convergence over manual refinements with fewer iterations from the layout team for automotive, communications, consumer electronics, enterprise computing, and industrial applications.
Manual workflows typically include numerous iterations of pipeline insertions, effort-intensive creation of constraints for physical placement of units, and lengthy NoC placement plus route iterations to converge on the SoC PPA targets. By contrast, FlexNoC 5 physical awareness eliminates these iterations and shortens the duration of various manual steps, facilitating up to 5X faster physical convergence of the back-end physical design time and effort. The resulting physically optimized NoC IP instance is then ready for output to physical synthesis and place and route for implementation.
Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect. Physical constraints have always been an important issue and are even more important below 16nm geometries. The latest FlexNoC 5 with its physical awareness technology, enables our RTL teams to verify that architectures meet physical constraints and provide a better starting point for our place and route team. We look forward to our continued cooperation with Arteris.“
Graham Curren, CEO of Sondrel.
