The Capital-Lite Semiconductor Model: Evolution of Semiconductor Startup Investment
Amer Haider, Vice President, Corporate and Business Development, Cavium
Awais Nemat, President and CEO, PLUMgrid, Inc. / Former Vice President, Enterprise Business, Marvell
The continued viability of VC funding for semiconductor
startups has been a subject of debate for the past few years.
A simple Google search on the phrase "VC model is broken"
yields hundreds of news articles, opinion pieces and research
papers analyzing the various reasons behind the weak returns of
VC investments, particularly those in the semiconductor sector.
Overfunding, limited exit opportunities and the exorbitant amount
of the initial investment required to reach cash flow breakeven in
VC-backed semiconductor startups are some of the reasons leading
to lackluster returns. This article analyzes the fundamental reasons
for the weakening of VC funding in the semiconductor industry and
proposes the Capital-Lite Semiconductor Model as a means to renew
investment interest in semiconductor startups.
The Capital-Lite Semiconductor Model enables startup
semiconductor companies to source intellectual property (IP)
and capital from more sizable semiconductor companies (i.e.,
$100 million+ revenues). Many sizable semiconductor companies
have been facing decreasing rates of revenue growth, while at the
same time accumulating large amounts of excess cash, as well as
substantial IP that can be monetized. Low growth rates have driven
these companies to search for additional sources of growth. The
Capital-Lite Semiconductor Model provides sizable semiconductor
companies with a way to drive growth by monetizing their IP and
creating acquisition opportunities, and to increase return on invested
capital by deploying their excess cash.
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For more information on the GSA Capital Lite Working Group,
click
here.
Determining The Optimal 3D IC Test Ecosystem
Dan Hamling, Senior Director, Business Development, IC Test and Assembly Equipment, GE Capital Global Electronics Services
The development of three-dimensional (3D) ICs continues to steal many of the headlines in the semiconductor industry as we head further into 2012. 3D ICs made IEEE Spectrum's Top Tech 2012 list, as well as EE Times' 20 Hot Technologies for 20121,2 (though barely making it in at number 20). A "hot" technology could imply many things, ranging from real and impactful, to catchy but fleeting. Based on the level of attention given to 3D ICs by key players in the industry, it seems that 3D ICs are the real deal and will be an important enabler for the consumer's insatiable appetite for more capability and bandwidth at lower costs and power. In terms of one growth metric, wafer bumping volume, Yole Development expects 3D ICs (as defined below) to grow from about five percent of total wafer bumping volume in 2012 to 27 percent of volume in 2016, resulting in a very steep compound annual growth rate (CAGR) of 84 percent3.
What is a 3D IC?
3D ICs may indeed be taking over the research and conference agendas as of late, but the use of the third dimension in chip packaging is not a new idea. Figure 1 visually describes the 3D package-on-package (PoP) and system-in-package (SiP) solutions that have been in high volume production in various configurations for several years now. These solutions were developed to address the same space, time-tomarket and technology integration demands as that of 3D ICs, but have encountered limitations with regard to bandwidth and power dissipation. Some configurations have height issues, as the thickness of mobile devices becomes increasingly important. The smartphone and tablet craze that surrounds us today was enabled in part by these first 3D packages.
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